Addressing Modes
Q2.
An array of 2 two byte integers is stored in big endian machine in byte addresses as shown below. What will be its storage pattern in little endian machine ? \begin{array}{c|c}\text{Address}& \text{Data}\\\hline0 \times 104&78\\0 \times 103&56\\0 \times 102&34\\0 \times 101&12\end{array}Q3.
The immediate addressing mode can be used for1. Loading internal registers with initial values 2. Perform arithmetic or logical operation on data contained in instructionsWhich of the following is true?Q4.
The most appropriate matching for the following pairs:\begin{array}{|l|l|l|l|} \hline \text{X.} & \text{Indirect Addressing} & i. & \text{Loop} \\ \hline \text{Y.} & \text{Immediate Addressing} & ii. & \text{Pointers} \\ \hline \text{Z.} & \text{Auto Decrement Addressing} & iii. & \text{Constants} \\ \hline \end{array}Q5.
Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC- relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence. If the target of the branch instruction is i, then the decimal value of the Offset is __________Q6.
Consider the C struct defined below: struct data { int marks [100] ; char grade; int cnumber; }; struct data student; The base address of student is available in register R1. The field student.grade can be accessed efficiently usingQ8.
For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3) An implied accumulator registerQ9.
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the Addressing Modes implemented by this instruction for the operand in memory?